http://insanity4004.blogspot.com/2019/04/simulating-vfd-gridanode-driver.html

Simulating the VFD Grid/Anode driver I was reading through an old posting about the VFD Grid and Anode driver circuit I’m planning to use, when it occurred to me that the resistor between the base of the PNP transistor and the collector of the NPN transistor might not be necessary. This is labeled R1 in the schematic to the right.

To calculate the desired resistance I’d done a bunch of hand calculations in my notebook, trying various combinations of target currents and resistor values. I started to do yet another with R1 set to zero when it occurred to me that this would be easier to do in simulation. At first I entered this circuit into LTspice using 2N3904 and 2N3906 transistors, as these are standard parts in the LTspice library. The simulation results matched my hand-calculated numbers, which gave me confidence that I’d done the calculations properly. I’m driving both transistors into saturation, and my turn-off times are anything but critical, so the choice of transistor isn’t critical. Then I wondered how closely this approximation matched the real Toshiba RN4604. At first I thought this would be a challenge, as the process for creating a Spice model description for a transistor from its datasheet isn’t that easy. Wouldn’t it be nice if Toshiba provided a Spice model? Well, they do, and it’s available for download from their website. To make it easier to probe the base current of Q1A (Q1 in the Spice schematic) I extracted the transistor models from the subcircuits that add the built-in bias resistors and substituted them into my circuit.

My original plan had been to turn on Q1A by passing about 500 µA through its base. This was based on the spec’d saturation ICE of 5 mA with IBE of 250 µA, giving an hFE of 20. In the actual application I’ve found a grid draws about 6 mA and its 10K pull-down resistor will draw another 3 mA, so I doubled IBE for an ICE of 10 mA. If I eliminate R1 the base current jumps to 606 µA. But this puts almost the full 30 volts across the input (between pins 1 and 2); the datasheet graphs stop with an input voltage of 9 V. Even with the original R1 of 10K the input voltage is almost 25 V. So I’m thinking I should revisit this.

Looking at the hFE graphs I see the worst-case (at -25°C!) current gain at 30 mA is about 100. Of course this is in the transistor’s linear region, but it implies that with a base current of 300 µA and a collector current of only 10 mA the thing will be saturated. So I tweaked my Spice simulation to sweep the value of R1 from 100 ohms to 150 Kohms. I graphed the base and collector currents of the transistor, along with the “input” voltage (the difference between pins 1 and 2 on the package). I also changed the collector load resistor to 1 KΩ to get about 30 mA collector current if the transistor was saturated. This would make it more obvious when decreasing the base drive would start having a significant effect on the collector current. The trick to interpreting these graphs is to remember that this is a PNP transistor in a common-emitter configuration, so the base and collector currents are negative. Thus a rise in the graph means less current. Also, the horizontal scale represents ohms, even though it’s reported in volts. So the “100KV” tick actually represents 100 KΩ.

It’s pretty obvious I don’t need 500 µA of base current. In fact, it looks like I could make R1 as high as 100 KΩ and still drive this transistor into saturation. Setting R1 to 63 KΩ gives me 250 µA of base current, while 47 KΩ gives me 295 µA. I’ll probably choose 47 KΩ to allow a generous margin for variations in bias resistor values, which can vary